LNAMIXENRFPKD=disable, IFADCCAPRESET=cap_reset_disable, IFADCENLDOSERIES=series_ldo_disable, LNAMIXLDOLOWCUR=regular_mode, SYPFDFPWENRX=disable, PGAENLDO=disable_ldo, SYCHPBIASTRIMBUFRX=i_tail_10u, LNAMIXENRFPKDLOTHRESH=disable, SYPFDCHPLPENRX=disable, LNAMIXREGLOADEN=disable_resistor, SYVCOVCAPFASTRAMPRX=vcap_fastramp_0, SYCHPQNC3EN=qnc_2, IFADCENLDOSHUNT=shunt_ldo_disable
| IFADCCAPRESET | IFADCCAPRESET 0 (cap_reset_disable): undefined 1 (cap_reset_enable): undefined |
| IFADCENLDOSERIES | IFADCENLDOSERIES 0 (series_ldo_disable): undefined 1 (series_ldo_enable): undefined |
| IFADCENLDOSHUNT | IFADCENLDOSHUNT 0 (shunt_ldo_disable): undefined 1 (shunt_ldo_enable): undefined |
| LNAMIXENRFPKD | LNAMIXENRFPKD 0 (disable): undefined 1 (enable): undefined |
| LNAMIXENRFPKDLOTHRESH | LNAMIXENRFPKDLOTHRESH 0 (disable): undefined 1 (enable): undefined |
| LNAMIXLDOLOWCUR | LNAMIXLDOLOWCUR 0 (regular_mode): undefined 1 (low_current_mode): undefined 3 (high_current_mode): undefined |
| LNAMIXREGLOADEN | LNAMIXREGLOADEN 0 (disable_resistor): undefined 1 (enable_resistor): undefined |
| PGAENLDO | PGAENLDO 0 (disable_ldo): undefined 1 (enable_ldo): undefined |
| SYCHPQNC3EN | SYCHPQNC3EN 0 (qnc_2): undefined 1 (qnc_3): undefined |
| SYCHPBIASTRIMBUFRX | SYCHPBIASTRIMBUFRX 0 (i_tail_10u): undefined 1 (i_tail_20u): undefined |
| SYPFDCHPLPENRX | SYPFDCHPLPENRX 0 (disable): undefined 1 (enable): undefined |
| SYPFDFPWENRX | SYPFDFPWENRX 0 (disable): undefined 1 (enable): undefined |
| SYVCOVCAPFASTRAMPRX | SYVCOVCAPFASTRAMPRX 0 (vcap_fastramp_0): undefined 1 (vcap_fastramp_1): undefined |